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october 2008 rev 2 1/17 1 L9822e octal serial solenoid driver features eight low r dson dmos outputs (0.5 @ i o = 1 a @ 25 c v cc = 5 v 5 %) 8 bit serial input data (spi) 8 bit serial diagnostic output for overload and open circuit conditions output short circuit protection chip enable select fu nction (active low) internal 36 v clamping for each output cascadable with another octal driver low quiescent current (10 ma max.) multipower bcd technology package multiwatt 15 and powerso-20 description the L9822e is an octal low-side solenoid driver realized in multipower bcd technology particularly suited for driving lamps, relays and solenoids in automotive environment. the dmos outputs L9822e has a very low power consumption. data is transmitted serially to the device using the serial peripheral interface (spi) protocol. status monitor function is available on all output lines. powerso-20 multiwatt 15 table 1. device summary order code package packing L9822e multiwatt 15 tube L9822epd powerso-20 tube www.st.com
contents L9822e 2/17 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 internal blocks description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 shift register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 parallel latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.4 output stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.5 timing data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.5.1 ce high to low transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.5.2 sclk transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.5.3 ce low to high transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.6 fault conditions check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
L9822e list of tables 3/17 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
list of figures L9822e 4/17 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. powerso-20 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. multiwatt 15 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. byte timing with asynchronous reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. powerso-20 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. multiwatt 15 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
L9822e block diagram 5/17 1 block diagram figure 1. block diagram parallel load clock fault reset 8 bit parallel latch reset input inputs + - outputs 1. . . . . 7 current limit fault reference voltage internal zener clamp fault indicators fault indicator parallel inputs serial input 8 bit shift register shift clock reset ce si so sclk q d ck q0 : : : q7 q7 : : : q0 d0 : : : d7 100s delay trigger output 01 02 03 04 05 output 0 00 06 07
pin description L9822e 6/17 2 pin description figure 2. powerso-20 pin connection (top view) figure 3. multiwatt 15 pin connection (top view) gnd so v cc reset out7 out5 out6 out4 n.c. n.c. out3 out2 out0 out1 ce sclk si gnd gnd gnd d94at119 10 8 9 7 6 5 4 3 2 13 14 15 16 17 19 18 20 12 1 11 1 2 3 4 5 6 7 9 10 11 8 reset vcc so gnd si sclk ce out 0 out 1 out 2 out 3 13 14 15 12 out 4 out 5 out 6 out 7 mult15
L9822e pin description 7/17 2.1 pin description table 2. pin function powerso20 pin # multiwatt15 pin # name function 1, 10, 11, 20 8 gnd device ground. this ground applies for the logic circuits as well as the power output stages. 29so serial output. this pin is the serial output from the shift register and it is tri-stated when ce is high. a high for a data bit on this pin indicates that the particular output is high. a low on this pin for a data bit indicates that the output is low. comparing the serial output bits with the previous serial input bits the external microcontroller implements the diagnostic data supplied by the L9822e. 310v cc logic supply voltage - nominally 5v. 4 11 reset asynchronous reset for the output stages, the parallel latch and the shift register inside the L9822e . this pin is active low and it must not be left floating. a power on clear function may be implemented connecting this pin to vcc with an external resistor and to ground with an external capacitor. 5-8, 13-16 1-4, 12-15 output 1-7 power output pins. the input and output bits corresponding to 07 are sent and received first via the spi bus and 00 is the last. the outputs are provided with current limiting and voltage sense functions for fault indication and protection. the nominal load current for these outputs is 500ma, but the current limiting is set to a minimum of 1.05a. the outputs also have on board clamps set at about 36v for recirculation of inductive load current. 9,12 - n.c. pins not connected. 17 5 ce chip enable. data is transferred from the shift registers to the outputs on the rising edge of this signal. the falling edge of this signal sets the shift register with the output voltage sense bits coming from the output stages. the output driver for the so pin is enabled when this pin is low. 18 6 sclk serial clock. this pin clocks the shift register. new so data will appear on every rising edge of this pin and new si data will be latched on every sclk?s falling edge into the shift register. 19 7 si serial input. this pin is the serial data input. a high on this pin will program a particular output to be off, while a low will turn it on.
electrical specifications L9822e 8/17 3 electrical specifications 3.1 absolute maximum ratings 3.2 thermal data 3.3 electrical characteristics table 3. absolute maximum ratings symbol parameter value unit v cc dc logic supply voltage ? 0.7 7 v v o output voltage ? 0.7 40 v i i input transient current (ce, si, sclk, reset, so): duration time t = 1 s, v i < 0 v i > v cc ? 25 + 25 ma i odc continuos output current (for each output) internally limited a t j , t stg junction and storage temperature range ? 40 150 c table 4. thermal data symbol parameter multiw att15 powerso20 unit r th j-case thermal resistance junction to case max. 2 1.5 c/w r th j-amb thermal resistance junction to ambient max. 35 60 c/w table 5. electrical characteristics (v cc = 5 v 5 %. t j = ? 40 to 125 c ; unless otherwise specified) symbol parameter test conditions min. typ. max. unit v oc output clamping volt. i o = 0.5 a, output programmed off 30 40 v e oc output clamping energy i o = 0.5 a, when on 20 mj i o leak output leakage current v o = 24 v, output programmed off 1 ma r dson on resistance output programmed on i o = 0.5 a i o = 0.8 a i o = 1 a with fault reset disabled 0.55 0.55 0.55 1 1 1 i ol output self limiting current output programmed on 1.05 a t phl turn-on delay i o = 500 ma no reactive load 10 s t p turn-off delay i o = 500 ma no reactive load 10 s
L9822e electrical specifications 9/17 v oref fault refer. voltage output progr. off fault detected if v o > v oref 1.6 2 v t ud fault reset delay (after ce l to h transition) see figure 6 . 75 250 s v off output off voltage output pin floating. output progr. off 1v input buffer (si, ce, sclk and reset pins) v t? threshold voltage at falling edge sclk only v cc = 5 v 10 % 0.2v cc 0.6 v v t+ threshold voltage at rising edge sclk only v cc = 5 v 10 % 0.7v cc 4.15 v v h hysteresis voltage v t+ ? v t? 0.85 2.5 v i i input current v cc = 5.50 v, 0 < v i < v cc ? 10 + 10 a c i input capacitance 0 < v i < v cc 20 pf output buffer (so pin) v sol output low voltage i o = 1.6 ma 0.4 v v soh output high voltage i o = 0.8 ma v cc ? 1.3v v i sotl output tristate leakage current 0 < v o < v cc , ce pin held high, v cc = 5.25 v ? 20 20 a c so output capacitance 0 < v o < v cc , ce pin held high 20 pf i cc quiescent supply current at v cc pin all outputs progr. on. i o = 0.5 a per output simultaneously 10 ma serial peripheral interface (see figure 5 , timing diagram) f op operating frequency d.c. 2 mhz t lead enable lead time 250 ns t lag enable lag time 250 ns t wsckh clock high time 200 ns t wsckl clock low time 200 ns t su data setup time 75 ns t h data hold time 75 ns t en enable time 250 ns t dis disable time 250 ns t v data valid time 100 ns t rso rise time (so output) v cc = 20 to 70 % c l = 200 pf 50 ns t fso fall time (so output) v cc = 70 to 20 % c l = 200 pf 50 ns t rsi rise time spi inputs (sck, si, ce) v cc = 20 to 70 % c l = 200 pf 200 ns t fsi fall time spi inputs (sclk, si, ce) v cc = 70 to 20 % c l = 200 pf 200 ns t ho output data hold time 0 s table 5. electrical characteristics (continued) (v cc = 5 v 5 %. t j = ? 40 to 125 c ; unless otherwise specified) symbol parameter test conditions min. typ. max. unit
functional description L9822e 10/17 4 functional description the L9822e dmos output is a low operating power device featuring, eight 1 r dson dmos drivers with transient protection circuits in output stages. each channel is independently controlled by an output latch and a common reset line which disables all eight outputs. the driver has low saturation and short circuit protection and can drive inductive and resistive loads such as solenoids, lamps and relays. data is transmitted to the device serially usi ng the serial peripheral interface (spi) protocol. the circuit receives 8 bit serial data by means of the serial input (si) which is stored in an internal register to control the output drivers. the serial output (so) provides 8 bit of diagnostic data representing the voltage level at the driver output. this allows the microprocessor to diagnose the condition of the output drivers. the output saturation voltage is monitored by a comparator for an out of saturation condition and is able to unlatch the particular driver through the fault reset line. this circuit is also cascadable with another octal driver in order to jam 8 bit multiple data. the device is selected when th e chip enable (ce) line is low. additionally the (so) is placed in a tri-state mode when the device is deselected. the negative edge of the (ce) transfers the voltage level of the drivers to the shift register and the positive edge of the (ce) latches the new data from the shift register to the drivers. when ce is low, data bit contained into the shift register is transferred to so output at every sclk positive transition while data bit present at si input is latched into the shift register on every sclk negative transition. 4.1 internal blocks description the internal architecture of the device is based on the three internal major blocks: 1. the octal shift register for talking to the spi bus, 2. the octal latch for holding control bits written into the device 3. the octal load driver array. 4.2 shift register the shift register has both serial and parallel inputs and serial and parallel outputs. the serial input accepts data from the spi bus and the serial output simultaneously sends data into the spi bus. the parallel outputs are latched into the parallel latch inside the L9822e at the end of a data transfer. the parallel inputs jam diagnostic data into the shift register at the beginning of a data transfer cycle. 4.3 parallel latch the parallel latch holds the input data from the shift register. this data then actuates the output stages. individual registers in the latch may be cleared by fault conditions in order to protect the overloaded output st ages. the entire latch may al so be cleared by the reset signal.
L9822e functional description 11/17 4.4 output stages the output stages provide an active low drive signal suitable for 0.75 a continuous loads. each output has a current limit circuit which limits the maximum output current to at least 1.05a to allow for high inrush currents. additionally, the outputs have internal zeners set to 36 volts to clamp inductive transients at turn-off. each output also has a voltage comparator observing the output node. if the voltage exceeds 1.8 v on an on output pin, a fault condition is assumed and the la tch driving this particular stage is reset, turning the output off to protect it. the timing of this action is described below. these comparators also provide diagnostic feedback data to the shift register. additionally, the comparators contain an internal pulldown current wh ich will cause the cell to indicate a low output voltage if the output is programmed off and the output pin is open circuited. 4.5 timing data transfer figure 5 shows the overall timing diagram from a byte transfer to and from the L9822e using the spi bus. 4.5.1 ce high to low transition the action begins when the chip enable (ce) pin is pulled low. the tri-state serial output (so) pin driver will be enabled en tire time that ce is low. at the falling edge of the ce pin, the diagnostic data from the voltage comparators in the out put stages will be latched into the shift register. if a particular out put is high, a logic one will be ja mmed into that bit in the shift register. if the output is low, a logic zero will be loaded there. the most significant bit (07) should be presented at the serial input (si) pin. a zero at th is pin will program an output on, while a one will progra m the output off. 4.5.2 sclk transitions the serial clock (sclk) pin should then be pulled high. at this point the diagnostic bit from the most significant output (07) will appear at the so pin. a high here indicates that the 07 pin is higher than 1.8 v. the sclk pin should then be toggled low then high. new so data will appear following every rising edge of sclk and new si data will be latched into the L9822e shift register on the falling edges. an unlimited amount of data may be shifted through the device shift register (into the si pin and out the so pin), allowing the other spi devices to be cascaded in a daisy chain with the L9822e. 4.5.3 ce low to high transition once the last data bit has been shifted into the L9822e, the ce pin should be pulled high. at the rising edge of ce the shift register data is latched into the parallel latch and the output stages will be actuated by the new data. an inter nal 160 s delay timer will also be started at this rising edge (see t ud ). during the 160ms period, the ou tputs will be protected only by the analog current limiting circuits since the resetting of the parallel latches by faults conditions will be inhibited during this period. this allows the part to overcome any high inrush currents that may flow immediately after turn on. once the delay period has elapsed, the output voltages are sensed by the comparators and any output with voltages higher than 1.8 v are latched off. it should be noted that the sclk pin should be low at both transitions of the ce pin to avoid any false clocking of the shift register. the sclk input is gated by the ce pin, so that the sclk pin is ignored whenever the ce pin is high.
functional description L9822e 12/17 4.6 fault conditions check checking for fault conditions may be done in the following way. clock in a new control byte. wait 160 s or so to allow the outputs to settle. clock in the same control byte and observe the diagnostic data that comes out of the device. the diagnostic bits should be identical to the bits that were first clocked in. any differences would point to a fault on that output. if the output was programmed on by clocking in a zero, and a one came back as the dia gnostic bit for that output, t he output pin was still high and a short circuit or overload condition exists. if the output was programmed off by clocking in a one, and a zero came back as the diagnostic bit for that output, nothing had pulled the output pin high and it must be floating, so an open circuit condition exists for that output. figure 4. byte timing with asynchronous reset. figure 5. timing diagram. reset ce sclk si #7 #6 #5 #4 #3 #2 #1 #7 #6 #5 #4 #3 #2 #1 #0 new reset faults so outputs old ce sclk si so outs old new tud tdis di0 tlag di7 th #6 #7 i/fop twsckh tlead #0 twsckl tsu tv ten thd d00 d06 d07 tphl tplh fault-induced turn/off
L9822e functional description 13/17 figure 6. typical application diagram lr micro controller with spi - bus v cc v bat ce 00 01 02 03 04 05 06 07 si so sclk reset v cc = 5.0 v +/- 5 % vbat = 14.0 v +/- 0.5 v r = 30 +/- 5 % l = 10mh +/- 10 % 8 loads up to 0.75 a each gnd L9822e
package information L9822e 14/17 5 package information in order to meet environmental requirements, st (also) offers these devices in ecopack ? packages. ecopack ? packages are lead-free. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 7. powerso-20 mechanical data and package dimensions outline and mechanical data e a2 a e a1 pso20mec detail a t d 110 11 20 e1 e2 h x 45? detail a lead slug a3 s gage plane 0.35 l detail b r detail b (coplanarity) gc - c - seating plane e3 b c n n h bottom view e3 d1 dim. mm inch min. typ. max. min. typ. max. a3.60.142 a1 0.1 0.3 0.004 0.012 a2 3.3 0.130 a3 0 0.1 0.000 0.004 b 0.4 0.53 0.016 0.021 c 0.23 0.32 0.009 0.013 d (1) 15.8 16 0.622 0.630 d1 (2 ) 9.4 9.8 0.370 0.386 e 13.9 14.5 0.547 0.570 e 1.27 0.050 e3 11.43 0.450 e1 (1) 10.9 11.1 0.429 0.437 e2 2.9 0.114 e3 5.8 6.2 0.228 0.244 g 0 0.1 0.000 0.004 h 15.5 15.9 0.610 0.626 h 1.1 0.043 l 0.8 1.1 0.031 0.043 n 8?(typ.) s 8?(max. ) t 10 0.394 (1) ?d and e1? do not include mold flash or protusions. - mold flash or protusions shall not exceed 0.15mm (0.006?) - critical dimensions: ?e?, ?g? and ?a3?. (2) for subcontractors, the limit is the one quoted in jedec mo-166 powerso-20 0056635 i jedec mo-166 weight: 1.9gr
L9822e package information 15/17 figure 8. multiwatt 15 mechanical data and package dimensions outline and mechanical data 0016036 j dim. mm inch min. typ. max. min. typ. max. a5 0.197 b 2.65 0.104 c 1.6 0.063 d 1 0.039 e 0.49 0.55 0.019 0.022 f 0.66 0.75 0.026 0.030 g 1.02 1.27 1.52 0.040 0.050 0.060 g1 17.53 17.78 18.03 0.690 0.700 0.710 h1 19.6 0.772 h2 20.2 0.795 l 21.9 22.2 22.5 0.862 0.874 0.886 l1 21.7 22.1 22.5 0.854 0.87 0.886 l2 17.65 18.1 0.695 0.713 l3 17.25 17.5 17.75 0.679 0.689 0.699 l4 10.3 10.7 10.9 0.406 0.421 0.429 l7 2.65 2.9 0.104 0.114 m 4.25 4.55 4.85 0.167 0.179 0.191 m1 4.73 5.08 5.43 0.186 0.200 0.214 s 1.9 2.6 0.075 0.102 s1 1.9 2.6 0.075 0.102 dia1 3.65 3.85 0.144 0.152 multiwatt15 (vertical)
revision history L9822e 16/17 6 revision history table 6. document revision history date revision changes 12-jan-2002 1 initial release. 27-oct-2008 2 document reformatted. corrected in table 5: electrical characteristics , the max. value of the parameter ?c i input capacitance?.
L9822e 17/17 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2008 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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